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flash memory 1 K9F1G08U0A k9f1g08q0a document title 128m x 8 bit nand flash memory revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you have any questions, please contact the samsung branch office near your office. revision no 0.0 0.1 0.2 0.3 remark advance preliminary preliminary history 1. initial issue 1. the tadl(address to data loading time) is added. - tadl minimum 100ns (page 11, 23~26) - tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle at program operation. 2. added addressing method for program operation 1. add the protrusion/burr value in wsop1 pkg diagram . 1. pkg(tsop1, wsop1) dimension change draft date aug . 24 . 200 3 jan. 27. 2004 apr. 23. 2004 may. 19. 2004
flash memory 2 K9F1G08U0A k9f1g08q0a general description features voltage supply -1.8v device( k9f1g08q0a ): 1.70v~1.95v -3.3v device( K9F1G08U0A ): 2.7 v ~3.6 v organization - memory cell array : (128m + 4,096k)bit x 8bit - data register : (2k + 64)bit x8bit - cache register : (2k + 64)bit x8bit automatic program and erase - page program : (2k + 64)byte - block erase : (128k + 4k)byte page read operation - page size : 2k-byte - random read : 25 m s(max.) - serial access : 30ns(min.) : (K9F1G08U0A) 50ns(min.) : (k9f1g08q0a) 128m x 8 bit nand flash memory fast write cycle time - program time : 300 m s(typ.) - block erase time : 2ms(typ.) command/address/data multiplexed i/o port hardware data protection - program/erase lockout during power transitions reliable cmos floating-gate technology - endurance : 100k program/erase cycles - data retention : 10 years command register operation cache program operation for high performance program intelligent copy-back operation unique id for copyright protection package : - K9F1G08U0A-ycb0/yib0 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - K9F1G08U0A-vib0 48 - pin wsop i (12x17x0.7mm) - K9F1G08U0A-pcb0/pib0 48 - pin tsop i (12 x 20 / 0.5 mm pitch)- pb-free package - K9F1G08U0A-fib0 48 - pin wsop i (12x17x0.7mm)- pb-free package * K9F1G08U0A -v,f(wsopi ) is the same device as K9F1G08U0A -y,p(tsop1) except package type. offered in 128mx8bit the k9f1g08x0a is 1g bit with spare 32m bit capacity. its nand cell provides the most cost-effective solution for the solid state mass storage market. a program operation can be performed in typical 300 m s on the 2112-byte page and an erase operation can be performed in typical 2ms on a 128k-byte block. data in the data page can be read out at 50ns (30ns, K9F1G08U0A) cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. the on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and m argin- ing of data. even the write-intensive systems can take advantage of the k9f1g08x0a s extended reliability of 100k program/erase cycles by providing ecc(error correcting code) with real time mapping-out algorithm. the k9f1g08x0a is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility . product list part number vcc range organization pkg type k9f1g08q0a 1.70 ~ 1.95v x8 only available in mcp K9F1G08U0A -y,p 2.7 ~ 3.6v tsop1 K9F1G08U0A -v,f wsop1
flash memory 3 K9F1G08U0A k9f1g08q0a pin configuration (tsop1) k9f1g08x0a-ycb0,pcb0/yib0,pib0 x8 x8 package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220af unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0 . 1 6 + 0 . 0 7 - 0 . 0 3 0 . 0 0 8 + 0 . 0 0 3 - 0 . 0 0 1 0 . 5 0 0 . 0 1 9 7 #48 #25 0 . 4 8 8 1 2 . 4 0 m a x 1 2 . 0 0 0 . 4 7 2 0 . 1 0 0 . 0 0 4 m a x 0 . 2 5 0 . 0 1 0 ( ) 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0 . 0 1 0 0 . 2 5 t y p 0 . 1 2 5 + 0 . 0 7 5 0 . 0 3 5 0 . 0 0 5 + 0 . 0 0 3 - 0 . 0 0 1 0.50 0.020 ( ) 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c 0 . 2 0 + 0 . 0 7 - 0 . 0 3
flash memory 4 K9F1G08U0A k9f1g08q0a pin configuration (wsop1) K9F1G08U0A-vib0,fib0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c dnu n.c n.c n.c r/b re ce dnu n.c vcc vss n.c dnu cle ale we wp n.c n.c dnu n.c n.c n.c n.c dnu n.c i/o7 i/o6 i/o5 i/o4 n.c dnu n.c vcc vss n.c dnu n.c i/o3 i/o2 i/o1 i/o0 n.c dnu n.c n.c package dimensions 48-pin lead plastic very very thin small out-line package type (i) 48 - wsop1 - 1217f unit :mm 15.40 0.10 #1 #24 0 . 2 0 + 0 . 0 7 - 0 . 0 3 0 . 1 6 + 0 . 0 7 - 0 . 0 3 0 . 5 0 t y p ( 0 . 5 0 0 . 0 6 ) #48 #25 0 . 1 0 + 0 . 0 7 5 - 0 . 0 3 5 17.00 0.20 0 ~ 8 0.45~0.75 1 2 . 0 0 0 . 1 0 0.58 0.04 0.70 max (0.01min) 1 2 . 4 0 m a x
flash memory 5 K9F1G08U0A k9f1g08q0a pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/ o pins float to high-z when the chip is deselected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for address to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode. re read enable the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent write/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. r/ b ready/busy output the r/ b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected.
flash memory 6 K9F1G08U0A k9f1g08q0a 2k bytes 64 bytes figure 1-1. k9f1g08x0a (x8) functional block diagram figure 2-1. k9f1g08x0a (x8) array organization note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than re q uired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 *l *l *l *l 3rd cycle a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 4th cycle a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 12 - a 27 a 0 - a 11 command ce re we cle wp i/0 0 i/0 7 v cc v ss 64k pages (=1,024 blocks) 2k bytes 8 bit 64 bytes 1 block = 64 pages (128k + 4k) byte i/o 0 ~ i/o 7 1 page = (2k + 64)bytes 1 block = (2k + 64)b x 64 pages = (128k + 4k) bytes 1 device = (2k+64)b x 64pages x 1024 blocks = 1056 mbits row address page register ale pre 1024m + 32m bit nand flash array (2048 + 64 )byte x 65536 y-gating cache register row address column address column address data register & s/a
flash memory 7 K9F1G08U0A k9f1g08q0a product introduction the k9f1g08x0a is a 1056mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2112x8 columns. spare 64 col- umns are located from column address of 2048~2111. a 2112-byte data register and a 2112-byte cache register are serially con- nected to each other. those serially connected registers are connected to memory cell arrays for accommodating data transfer between the i/o buffers and memory cells during page read and page program operations. the memory array is made up of 32 cells that are serially connected to form a nand structure. each of the 32 cells resides in a different page. a block consists of two nand structured strings. a nand structure consists of 32 cells. total 1081344 nand cells reside in a block. the program and read opera- tions are executed on a page basis, while the erase operation is executed on a block basis. the memory array consists of 1024 se p- arately erasable 128k-byte blocks. it indicates that the bit by bit erase operation is prohibited on the k9f1g08x0a . the k9f1g08x0a has addresses multiplexed into 8 i/os. this scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. command, address and data are all written through i/o's b y bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. some commands require one bus cycle. for example, reset command, status read command, etc require just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. the 128m byte physical space requires 28 addresses, thereby requiring four cycles for addressing: 2 cycles of column address, 2 cycles of row address, in that order. page read and page program need the same four address cycles following the required command input. in block erase oper- ation, however, only the two row address cycles are used. device operations are selected by writing specific commands into the c om- mand register. table 1 defines the specific commands of the k9f1g08x0a . the device provides cache program in a block. it is possible to write data into the cache registers while data stored in data re gisters are being programmed into memory cells in cache program mode. the program performace may be dramatically improved by cache program when there are lots of pages of data to be programmed. in addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to anoth er page without need for transporting the data to and from the external buffer memory. since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased. table 1. command sets note : 1. random data input/output can be executed in a page. 2. command not specified in command sets table is not permitted to be entered to the device, which can raise errone ous operation. function 1st. cycle 2nd. cycle acceptable command during busy read 00h 30h read for copy back 00h 35h read id 90h - reset ffh - o page program 80h 10h cache program 80h 15h copy-back program 85h 10h block erase 60h d0h random data input * 85h - random data output * 05h e0h read status 70h o caution : any undefined command inputs are prohibited except for above command set of table 1.
flash memory 8 K9F1G08U0A k9f1g08q0a recommended operating conditions (voltage reference to gnd, k9f1g08x0a -xcb0 : t a =0 to 70 c, k9f1g08x0a -xib0 : t a =-40 to 85 c) parameter symbol k9f1g08q0a(1.8v) K9F1G08U0A(3.3v) unit min typ. max min typ. max supply voltage v cc 1.70 1.8 1.95 2.7 3.3 3.6 v supply voltage v ss 0 0 0 0 0 0 v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc, +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit 1.8v device 3.3v / 2.65v device voltage on any pin relative to v ss v in/out -0.6 to + 2.45 -0.6 to + 4.6 v v cc -0.2 to + 2.45 -0.6 to + 4.6 temperature under bias k9f1g08x0a -xcb0 t bias -10 to +125 c k9f1g08x0a -xib0 -40 to +125 storage temperature k9f1g08x0a -xcb0 t stg -65 to +150 c k9f1g08x0a -xib0 short circuit current ios 5 ma
flash memory 9 K9F1G08U0A k9f1g08q0a dc and operating characteristics (recommended operating conditions otherwise noted.) note : v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less. parameter symbol test conditions k9f1g08q0a K9F1G08U0A unit 1.8v 3.3v min typ max min typ max operating current page read with serial access i cc 1 trc= 5 0ns, ce =v il i out =0ma - 10 20 - 1 5 3 0 ma program i cc 2 - - 10 20 - 1 5 3 0 erase i cc 3 - - 10 20 - 1 5 3 0 stand-by current(ttl) i sb 1 ce =v ih , wp =0v/v cc - - 1 - - 1 stand-by current(cmos) i sb 2 ce =v cc -0.2, wp =0v/v cc - 1 0 5 0 - 10 50 m a input leakage current i li v in =0 to vcc(max) - - 1 0 - - 1 0 output leakage current i lo v out =0 to vcc(max) - - 1 0 - - 1 0 input high voltage v ih * - 0.8x v cc - v cc +0.3 0.8xvcc - v cc +0.3 v input low voltage, all inputs v il * - -0.3 - 0.2xvcc -0.3 - 0.2xvcc output high voltage level v oh k9f1g08q0a :i oh =-100 m a K9F1G08U0A :i oh =-400 m a vcc -0.1 - - 2.4 - - output low voltage level v ol k9f1g08q0a :i ol =100ua K9F1G08U0A :i ol =2.1ma - - 0.1 - - 0.4 output low current(r/ b ) i ol (r/ b ) k9f1g08q0a :v ol =0.1v K9F1G08U0A :v ol =0.4v 3 4 - 8 10 - ma
flash memory 10 K9F1G08U0A k9f1g08q0a capacitance ( t a =25 c, v cc =1.8v/3.3v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. the k9f1g08x0a may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid blocks is presented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits. do not erase or program factory-marked bad blocks . refer to the attached technical notes for appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require error correction up to 1k program/erase cycles. parameter symbol min typ. max unit valid block number n vb 1004 - 1024 blocks ac test condition ( k9f1g08x0a -xcb0 :ta=0 to 70 c, k9f1g08x0a -xib0:ta=-40 to 85 c k9f1g08q0a : vcc=1.70v~1.95v, K9F1G08U0A : vcc=2.7v~3.6v unless otherwise noted) parameter k9f1g08q0a K9F1G08U0A input pulse levels 0v to vcc 0v to vcc input rise and fall times 5ns 5ns input and output timing levels vcc/2 vcc/2 output load 1 ttl gate and cl=30pf 1 ttl gate and cl=50pf mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode h l l h x read mode command input l h l h x address input(4clock) h l l h h write mode command input l h l h h address input(4clock) l l l h h data input l l l h x data output x x x x h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect x x h x x 0v/v cc (2) stand-by
flash memory 11 K9F1G08U0A k9f1g08q0a program / erase characteristics note : 1. max. time of t cbsy depends on timing between internal program completion and data in parameter symbol min typ max unit program time t prog - 300 700 m s dummy busy time for cache program t cbsy 3 700 m s number of partial program cycles in the same page main array nop - - 4 cycles spare array - - 4 cycles block erase time t bers - 2 3 ms ac timing characteristics for command / address / data input note : 1. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. parameter symbol min max unit k9f1g08q0a K9F1G08U0A k9f1g08q0a K9F1G08U0A cle setup time t cls 25 10 - - ns cle hold time t clh 10 5 - - ns ce setup time t cs 35 15 - - ns ce hold time t ch 10 5 - - ns we pulse width t wp 25 15 - - ns ale setup time t als 25 10 - - ns ale hold time t alh 10 5 - - ns data setup time t ds 20 10 - - ns data hold time t dh 10 5 - - ns write cycle time t wc 45 30 - - ns we high hold time t wh 15 10 - - ns ale to data loading time t adl 100 (1) 100 (1) - - ns
flash memory 12 K9F1G08U0A k9f1g08q0a ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us. parameter symbol min max unit k9f1g08q0a K9F1G08U0A k9f1g08q0a K9F1G08U0A data transfer from cell to register t r - - 25 25 m s ale to re delay t ar 10 10 - - ns cle to re delay t clr 10 10 - - ns ready to re low t rr 20 20 - - ns re pulse width t rp 25 15 - - ns we high to busy t wb - - 100 100 ns read cycle time t rc 50 30 - - ns re access time t rea - - 30 18 ns ce access time t cea - - 45 23 ns re high to output hi-z t rhz - - 30 30 ns ce high to output hi-z t chz - - 20 20 ns re or ce high to output hold t oh 15 15 - - ns re high hold time t reh 15 10 - - ns output hi-z to re low t ir 0 0 - - ns we high to re low t whr 60 60 - - ns device resetting time (read/program/erase) t rst - - 5/10/500 (1) 5/10/500 (1) m s
flash memory 13 K9F1G08U0A k9f1g08q0a nand flash technical notes identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. the i nfor- mation regarding the invalid block(s) is so called as the invalid block information. devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the perf or- mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. the system d esign must be able to mask out the invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is guara n- teed to be a valid block, does not require error correction up to 1k program/erase cycles. all device locations are erased(ffh) except locations where the invalid block(s) information is written prior to shipping. the i nvalid block(s) status is defined by the 1st byte in the spare area. samsung makes sure that either the 1st or 2nd page of every invali d block has non-ffh data at the column address of 2048. since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recognize the invalid block (s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(figure 3). any intentional erasure of the original invalid block information is prohibited. * check "ffh" at the column address figure 3. flow chart to create invalid block table. start set block address = 0 check "ffh increment block address last block ? end no yes yes create (or update) no invalid block(s) table of the 1st and 2nd page in the block 2048
flash memory 14 K9F1G08U0A k9f1g08q0a nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? write 00h i/o 0 = 0 ? no * if ecc is used, this verification write 80h write address write data write 10h read status register write address wait for tr time verify data fail program completed or r/b = 1 ? program error yes no yes * program error pass : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * operation is not needed. error in write or read operation within its life time, additional invalid blocks may develop with nand flash memory. refer to the qualification report for the ac tual data.the following possible failure modes should be considered to implement a highly reliable system. in the case of status read fail- ure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block.to improve the efficiency of me m- ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ecc without any block replacement. the said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read back ( verify after program) --> block replacement or ecc correction read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection write 30h
flash memory 15 K9F1G08U0A k9f1g08q0a erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) write 30h block replacement buffer memory of the controller. 1st block a block b (n-1)th nth (page) { ~ 1st (n-1)th nth (page) { ~ an error occurs. 1 2 * step1 when an error happens in the nth page of the block ?a? during erase or program operation. * step2 copy the data in the 1st ~ (n-1)th page to the same location of another free block. (block ?b?) * step3 then, copy the nth page data of the block ?a? in the buffer memory to the nth page of the block ?b?. * step4 do not erase or program to block ?a? by creating an ?invalid block? table or other appropriate scheme.
flash memory 16 K9F1G08U0A k9f1g08q0a within a block, the pages must be programmed consecutively from the lsb (least significant bit) page of the block to msb (most s ig- nificant bit) pages of the block. random page address programming is prohibited. from the lsb page to msb page data in: data (1) data (64) (1) (2) (3) (32) (64) data register page 0 page 1 page 2 page 31 page 63 ex.) random page program (prohibition) data in: data (1) data (64) (2) (32) (3) (1) (64) data register page 0 page 1 page 2 page 31 page 63 nand flash technical notes (continued) addressing for program operation : : : :
flash memory 17 K9F1G08U0A k9f1g08q0a system interface using ce don?t-care. for an easier system interface, ce may be inactive during the data-loading or serial access as shown below. the internal 2112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. in addition, for vo ice or audio applications which use slow cycle time on the order of u-seconds, de-activating ce during the data-loading and serial access would provide significant savings in power consumption. figure 4. program operation with ce don?t-care. ce we t wp t ch address(4cycles) 80h data input ce cle ale we data input ce don?t-care 10h address(4cycle) 00h ce cle ale we data output(serial access) ce don?t-care r/ b t r re t cea out ce re i/o 0 ~ 7 figure 5. read operation with ce don?t-care. 30h i/ox i/ox ? ? ? t rea t cs
flash memory 18 K9F1G08U0A k9f1g08q0a command latch cycle ce we cle ale command address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh ce we cle ale col. add1 t cls t cs t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t alh t ds t dh t wp note device i/o data address i/ox data in/out col. add1 col. add2 row add1 row add2 k9f1g08x0a i/o 0 ~ i/o 7 ~2112byte a0~a7 a8~a11 a12~a19 a20~a27 i/ox i/ox col. add2 row add1 row add2 t wc
flash memory 19 K9F1G08U0A k9f1g08q0a input data latch cycle ce cle we din 0 din 1 din final* ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp ? ? ? i/ox ? ? ? notes : din final means 2112 re ce r/ b i/ox ? ? t rr t cea t rea t rp t reh t rea t rc t rhz* ? ? t rea dout t oh dout dout t oh t rhz* t chz* s erial access cycle after read (cle=l, we =h, ale=l) notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested.
flash memory 20 K9F1G08U0A k9f1g08q0a status read cycle ce we cle re 70h status output t clr t clh t cs t wp t ch t ds t dh t rea t ir* t oh t oh t whr t cea t cls i/ox t chz* t rhz*
flash memory 21 K9F1G08U0A k9f1g08q0a read operation (intercepted by ce ) ce cle r/ b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h read operation ce cle r/ b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc ? ? ? row add2 30h t clr i/ox i/ox col. add1 col. add2 row add1 row add2 t oh t oh
flash memory 22 K9F1G08U0A k9f1g08q0a t c l r r a n d o m d a t a o u t p u t i n a p a g e c e c l e r / b w e a l e r e b u s y 0 0 h d o u t n d o u t n + 1 r o w a d d r e s s c o l u m n a d d r e s s t w b t a r t r t r r t r c 3 0 h 0 5 h c o l u m n a d d r e s s d o u t m d o u t m + 1 e 0 h i / o x c o l . a d d 1 c o l . a d d 2 r o w a d d 1 r o w a d d 2 c o l a d d 1 c o l a d d 2 t w h r t r e a
flash memory 23 K9F1G08U0A k9f1g08q0a m = 2112byte page program operation ce cle r/ b we ale re 80h 70h i/o 0 din n din 10h m serialdata input command column address row address 1 up to m byte serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc ? ? ? ? i/ox co.l add1 col. add2 row add1 row add2 t adl notes : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle.
flash memory 24 K9F1G08U0A k9f1g08q0a p a g e p r o g r a m o p e r a t i o n w i t h r a n d o m d a t a i n p u t c e c l e r / b w e a l e r e 8 0 h 7 0 h i / o 0 d i n n d i n 1 0 h m s e r i a l d a t a i n p u t c o m m a n d c o l u m n a d d r e s s r o w a d d r e s s s e r i a l i n p u t p r o g r a m c o m m a n d r e a d s t a t u s c o m m a n d t p r o g t w b t w c t w c ? ? ? ? 8 5 h r a n d o m d a t a i n p u t c o m m a n d c o l u m n a d d r e s s t w c d i n j d i n k s e r i a l i n p u t ? ? i / o x c o l . a d d 1 c o l . a d d 2 r o w a d d 1 r o w a d d 2 c o l . a d d 1 c o l . a d d 2 r o w a d d 3 ? t a d l n o t e s : t a d l i s t h e t i m e f r o m t h e w e r i s i n g e d g e o f f i n a l a d d r e s s c y c l e t o t h e w e r i s i n g e d g e o f f i r s t d a t a c y c l e . t a d l
flash memory 25 K9F1G08U0A k9f1g08q0a c o p y - b a c k p r o g r a m o p e r a t i o n w i t h r a n d o m d a t a i n p u t c e c l e r / b w e a l e r e 0 0 h 7 0 h i / o 0 8 5 h c o l u m n a d d r e s s r o w a d d r e s s r e a d s t a t u s c o m m a n d i / o 0 = 0 s u c c e s s f u l p r o g r a m i / o 0 = 1 e r r o r i n p r o g r a m t p r o g t w b t w c b u s y t w b t r b u s y 1 0 h c o p y - b a c k d a t a i n p u t c o m m a n d 3 5 h c o l u m n a d d r e s s r o w a d d r e s s d a t a 1 d a t a n i / o x c o l a d d 1 c o l a d d 2 r o w a d d 1 r o w a d d 2 c o l a d d 1 c o l a d d 2 r o w a d d 1 r o w a d d 2 ? ? ? ? n o t e s : t a d l i s t h e t i m e f r o m t h e w e r i s i n g e d g e o f f i n a l a d d r e s s c y c l e t o t h e w e r i s i n g e d g e o f f i r s t d a t a c y c l e . t a d l ?
flash memory 26 K9F1G08U0A k9f1g08q0a c a c h e p r o g r a m o p e r a t i o n ( a v a i l a b l e o n l y w i t h i n a b l o c k ) c e c l e r / b w e a l e r e 8 0 h d i n n d i n 1 5 h m s e r i a l d a t a i n p u t c o m m a n d c o l u m n a d d r e s s s e r i a l i n p u t p r o g r a m m a x . 6 3 t i m e s r e p e a t a b l e t c b s y t w b t w c ? ? ? ? c o m m a n d l a s t p a g e i n p u t & p r o g r a m t c b s y : m a x . 7 0 0 u s ( d u m m y ) d i n n d i n 1 0 h t p r o g t w b ? ? ? i / o 8 0 h c o l a d d 1 , 2 & r o w a d d 1 , 2 r / b d a t a a d d r e s s & d a t a i n p u t 1 5 h 8 0 h a d d r e s s & d a t a i n p u t 1 5 h 8 0 h a d d r e s s & d a t a i n p u t 1 5 h 8 0 h a d d r e s s & d a t a i n p u t 1 0 h e x . ) c a c h e p r o g r a m t c b s y t c b s y t c b s y t p r o g p r o g r a m c o n f i r m c o m m a n d ( t r u e ) 8 0 h 7 0 h 7 0 h m r o w a d d r e s s i / o x i / o x c o l a d d 1 c o l a d d 2 r o w a d d 1 r o w a d d 2 c o l a d d 1 c o l a d d 2 r o w a d d 1 r o w a d d 2 ? n o t e s : t a d l i s t h e t i m e f r o m t h e w e r i s i n g e d g e o f f i n a l a d d r e s s c y c l e t o t h e w e r i s i n g e d g e o f f i r s t d a t a c y c l e . t a d l t a d l
flash memory 27 K9F1G08U0A k9f1g08q0a block erase operation ce cle r/ b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc auto block erase setup command i/ox row add1 row add2 ?
flash memory 28 K9F1G08U0A k9f1g08q0a read id operation ce cle we ale re 90h read id command maker code device code 00h ech device t rea address. 1cycle xxh 4th cyc.* i/ox t ar device device code*(2nd cycle) 4th cycle* k9f1g08q0a a1h 15h K9F1G08U0A f1h 15h code* id defintition table 90 id : access command = 90h description 1 st byte 2 nd byte 3 rd byte 4 th byte maker code device code don?t care page size, block size, spare size, organization,serial access minimum
flash memory 29 K9F1G08U0A k9f1g08q0a 4th id data item description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (w/o redundant area ) 1kb 2kb reserved reserved 0 0 0 1 1 0 1 1 block size (w/o redundant area ) 64kb 128kb 256kb reserved 0 0 0 1 1 0 1 1 redundant area size ( byte/512byte) 8 16 0 1 organization x8 x16 0 1 serial access minimum 50ns 25ns reserved reserved 0 1 0 1 0 0 1 1
flash memory 30 K9F1G08U0A k9f1g08q0a device operation page read page read is initiated by writing 00h-30h to the command register along with five address cycles. after initial power up, 00h co mmand is latched. therefore only five address cycles and 30h command initiates that operation after initial power up. the 2112 bytes of data within the selected page are transferred to the data registers in less than 25 m s(t r ). the system controller can detect the completion of this data tr ansfer(tr) by analyzing the output of r/ b pin. once the data in a page is loaded into the data reg- isters, they may be read out in 50ns (30ns, K9F1G08U0A) cycle time by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device output the data starting from the selected column address up to the last column address. the device may output random data in a page instead of the consecutive sequential data by writing random data output command. the column address of next data, which is going to be out, may be changed to the address which follows random data output com- mand. random data output can be operated multiple times regardless of how many times it is done in a page. figure 6. read operation address(4cycle) 00h col add1,2 & row add1,2 data output(serial access) data field spare field ce cle ale r/ b we re t r 30h i/ox
flash memory 31 K9F1G08U0A k9f1g08q0a figure 7. random data output in a page address 00h data output r/ b re t r 30h address 05h e0h 4cycles 2cycles data output data field spare field data field spare field page program the device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive bytes up to 2112, in a single page program cycle. the number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare array(1time/16byte). the addressing should be done in sequential order in a block. a page program cycle consists of a serial dat a loading period in which up to 2112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input command(80h), followed by the four cycle address inputs and then serial data loading. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address of next data, which will be entered, may be changed to the address which follows random data input command(85h). random data input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command(10h) initiates the programming process. writing 10h alone without previously entering the serial data will not initiate the programming process. the internal write state controller automatically executes the algorithms and tim- ings necessary for program and verify, thereby freeing the system controller for other tasks. once the program process starts, t he read status register command may be entered to read the status register. the system controller can detect the completion of a p ro- gram cycle by monitoring the r/ b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit(i/o 0) may be checked(figure 8). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the comm and register remains in read status command mode until another valid command is written to the command register. figure 8. program & read status operation 80h r/ b address & data input i/o 0 pass data 10h 70h fail t prog i/ox i/ox col add1,2 & row add1,2 "0" "1" col add1,2 & row add1,2
flash memory 32 K9F1G08U0A k9f1g08q0a cache program figure 9. random data input in a page 80h r/ b address & data input i/o 0 pass 10h 70h fail t prog 85h address & data input cache program is an extension of page program, which is executed with 2112byte data registers, and is available only within a bl ock. since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell. after writing the first set of data up to 2112byte into the selected cache registers, cache program command (15h) instead of act ual page program (10h) is inputted to make cache registers free and to start internal program operation. to transfer data from cache reg- isters to data registers, the device remains in busy state for a short period of time(tcbsy) and has its cache registers ready f or the next data-input while the internal programming gets started with the data loaded into data registers. read status command (70h) may be issued to find out when cache registers become ready by polling the cache-busy status bit(i/o 6). pass/fail status of only th e pre- viouse page is available upon the return to ready state. when the next set of data is inputted with the cache program command, tcbsy is affected by the progress of pending internal programming. the programming of the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. the status bit(i/ o5) for internal ready/busy may be polled to identify the completion of internal programming. if the system monitors the progres s of programming only with r/ b , the last page of the target programming sequence must be progammed with actual page program com- mand (10h). figure 10. cache program (available only within a block) 80h r/ b 80h address & data input 15h 80h address & data input 15h 80h address & data input 10h t cbsy t cbsy t cbsy t prog 70h address & data input* 15h i/ox col add1,2 & row add1,2 col add1,2 data data col add1,2 & row add1,2 col add1,2 & row add1,2 col add1,2 & row add1,2 data data data col add1,2 & row add1,2 data "0" "1"
flash memory 33 K9F1G08U0A k9f1g08q0a copy-back program figure 11. page copy-back program operation 00h r/ b add.(4cycles) i/o 0 pass 85h 70h fail t prog add.(4cycles) t r source address destination address the copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external mem ory. since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. the ben- efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly as signed free block. the operation for performing a copy-back program is a sequential execution of page-read without serial access and co py- ing-program with the address of destination page. a read operation with "35h" command and the address of the source page moves the whole 2112byte data into the internal data buffer. as soon as the device returns to ready state, page-copy data-input comman d (85h) with the address cycles of destination page followed may be written. the program confirm command (10h) is required to actu - ally begin the programming operation. data input cycle for modifying a portion or multiple distant portions of the source page i s allowed as shown in figur e 12. "when there is a program-failure at copy-back operation, error is reported by pass/fail status. but if the soure page has a bit error for charge loss, accumulated copy-back operations could also accumulate bit errors. for this reas on, two bit ecc is recommended for copy-back operation." 35h note : since programming the last page does not employ caching, the program time has to be that of page program. however, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only aft er com- pletion of the previous cycle, which can be expressed as the following formula. tprog= program time for the last page+ program time for the ( last -1 )th page - (program command cycle time + last page data loading time) 10h figure 12. page copy-back program operation with random data input 00h r/ b add.(4cycles) 85h 70h t prog add.(4cycles) t r source address destination address data 35h 10h 85h data add.(2cycles) there is no limitation for the number of repetition. i/ox i/ox col. add1,2 & row add1,2 col. add1,2 & row add1,2 col. add1,2 & row add1,2 col. add1,2 & row add1,2 col add1,2
flash memory 34 K9F1G08U0A k9f1g08q0a figure 13. block erase operation block erase the erase operation is done on a block basis. block address loading is accomplished in two cycles initiated by an erase setup co m- mand(60h). only address a 18 to a 27 is valid while a 12 to a 17 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution command ensures th at memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. when the erase operation is completed, the write status bit(i/o 0) may be checked. figure 13 details the sequence. 60h block add. : a 12 ~ a 27 r/ b address input(2cycle) i/o 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. after writing 70h command to the command register, a read cycle output s the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random r ead cycle, the read command(00h) should be given before starting read cycles. table2. read staus register definition note : 1. true ready/busy represents internal program operation status which is being executed in cache program mode. 2. i/os defined ?not use? are recommended to be masked out when read status is being executed. i/o no. page program block erase cache prorgam read definition i/o 0 pass/fail pass/fail pass/fail(n) not use pass : "0" fail : "1" i/o 1 not use not use pass/fail(n-1) not use pass : "0" fail : "1" i/o 2 not use not use not use not use "0" i/o 3 not use not use not use not use "0" i/o 4 not use not use not use not use "0" i/o 5 ready/busy ready/busy true ready/busy ready/busy busy : "0" ready : "1" i/o 6 ready/busy ready/busy ready/busy ready/busy busy : "0" ready : "1" i/o 7 write protect write protect write protect write protect protected:"0" not protected:"1" i/ox "0" "1"
flash memory 35 K9F1G08U0A k9f1g08q0a figure 14. read id operation ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. four read cycles sequentially output the manufacturer code(ech), and the device code and xxh, 4th cycle id, respectively. the command register remains in read id mode until further commands are issued to it. figure 14 shows the operation sequence. device xxh 4th cyc.* ech figure 15. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during rand om read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 3 for device status after reset operation. if the device is already in reset state a new reset command will be accepted by the command register. the r/ b pin transitions to low for trst after the reset command is written. refer to figure 15 below. ffh i/o x r/ b t rst t whr t clr code* device device code*(2nd cycle) 4th cycle* k9f1g08q0a a1h 15h K9F1G08U0A f1h 15h table3. device status after power-up after reset operation mode 00h command is latched waiting for next command
flash memory 36 K9F1G08U0A k9f1g08q0a ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. because pull-up resistor value is related to tr(r/ b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(fig 17). its value c an be determined by the following guidance. v cc r/ b open drain output device gnd rp figure 17. rp vs tr ,tf & rp vs ibusy ibusy busy ready vcc voh tf tr vol 1.8v device - v ol : 0.1v, v oh : v cc -0.1v 3.3v device - v ol : 0.4v, v oh : 2.4v c l tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 1.7 1.7 1.7 1.7 1.7 0.85 0.57 0.43 tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 c , c l = 50pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 50 tf 100 150 200 1.8 1.8 1.8 1.8 2.4 1.2 0.8 0.6 rp(min, 1.8v part) = v cc (max.) - v ol (max.) i ol + s i l = 1.85v 3ma + s i l where i l is the sum of the input currents of all devices tied to the r/ b pin. rp value guidance rp(max) is determined by maximum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + s i l = 3.2v 8ma + s i l
flash memory 37 K9F1G08U0A k9f1g08q0a data protection & power up sequence the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 1.1v(1.8v device), 1.8v(2.65v device), 2v(3.3v device). wp pin provides hard- ware protection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 10 m s is required before internal circuit gets ready for any command sequences as shown in figure 17. the two step command sequence for program/erase provides additional software protection. figure 17. ac waveforms for power transition v cc wp high we 1.8v device : ~ 1.5v 3.3v device : ~ 2.5v 1.8v device : ~ 1.5v 3.3v device : ~ 2.5v 10 m s ? ? ? ?

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